1. Field of the Invention
The present invention relates to a multiple interrupt controller and control method using an intelligent priority-decision mechanism thereof in which a plurality of input/output (I/O) devices can multiplexedly use a single interrupt line in the environment in which a host bus uses limited interrupt resources within a computer system.
2. Description of the Prior Art
Today's trend is that various input/output (I/O) device chips are miniaturized, high integrated and are required to be equipped with multi-functions such as multimedia applications. In a computer system, most input/output (I/O) devices typically process data in itself and then send them to main memory or other input/output devices. At this time, to request the main processor to do the job, I/O devices use an interrupt. In this case, there is no problem in case that a single interrupt line is allocated to a single input/output device each by each. However, as mentioned above, in recent years, as multi-function chip or multi-function board are commonly used, the hardware resources in a single chip or in a single board desiring to use interrupts over a host bus are increased, and accordingly in many cases, many interrupt users have to share the single interrupt line of the host bus. In this environments, it is likely to be inefficient utilization of interrupt resources that the I/O device which adopts the highest priority uses interrupts almost exclusively, and the I/O devices which adopt the lowest priority tend to be starved etc.
In a conventional computer system, the input/output devices connected to Pended bus are in most cases allocated to only one interrupt. In recent years, in most cases since more than one interrupt generating resources connected to the bus exist within a single chip or single board due to miniaturization of chip, higher integration, and multi function of system, there are problems in handling and sharing an interrupt in this case. The problems that may occur in handling and sharing an interrupt include; a time delay of handling interrupt which is caused by the fact that more than one interrupts must be transmitted via a single pended interrupt line, and an interrupt starvation phenomenon due to fixed interrupt priority etc.